Sources of Leakage Currents in Nanometer CMOS

There are five major sources of leakage currents in CMOS transistors, they are:

• Gate oxide tunnelling leakage (I_G)
• Subthreshold leakage (I_SUB)
• Reverse-bias junction leakages (I_REV)
• Gate Induced Drain Leakage (I_GIDL)
• Gate current due to hot-carrier injection (I_H)

Gate oxide tunnelling leakage

The downscaling of the gate oxide thickness increases the field oxide across the gate resulting to electron tunnelling from gate to substrate or from substrate to gate. The resulting current is called gate oxide tunnelling current and it is the major leakage current in the nanometer CMOS. Two mechanisms are responsible for this phenomenon. The first is called Fowler-Nordheim (FN) tunnelling mechanism, which is electron tunnelling into the conduction band of the oxide layer.  The other mechanism, direct tunnelling, is more dominant than the FN.  In this case, electron tunnel directly to the gate through the forbidden energy gap of the silicon dioxide layer.  The resulting current is called the gate direct-tunnelling leakage and it flows from the gate through the oxide insulation to the substrate.

Subthreshold leakage

The subthreshold leakage is the drain-source current of a transistor during operation in weak inversion (where transistors switch ON though the gate source voltage is below the threshold voltage, the voltage at which when exceeded the transistor is expected to be turned ON). Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a metal oxide semiconductor (MOS) device. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters.

Reverse-bias source/drain junction leakages

Though the p-n junctions between the source/drain and the substrate are reverse-biased, yet a small amount of current flows causing these junctions to leak. This current is called reverse biased junction leakage current. The magnitude of this current depends on the area of the source/drain diffusion and the current density, which is in turn determined by the doping concentration. The highly doped shallow junctions and halo doping necessary to control short channel effects (SCE) in the nanometer devices has escalated this leakage current. Under this situation, electrons tunnel across the p-n junction causing junction leakage.

Gate Induced Drain Leakage (GIDL)

This leakage current is caused by high electric field effect in the drain junction of MOS transistors. Over the years, transistor scaling has led to increasingly steep halo implants, where the substrate doping at the junction interfaces is increased, while the channel doping is low. Its purpose is to control punch-through and drain-induced barrier lowering with minimal impact on the mobility of the carrier in the channel. The steep doping profile that results at the drain edge increases the band-to-band tunnelling currents there, especially as drain-bulk voltage (V_db) is increased. Thinner oxide and higher supply voltage increase GIDL current. Controlling the doping concentration in the drain of the transistor is the best way to control GIDL.

Gate current due to hot-carrier injection (I_H)

This leakage current is due to drift over time of the threshold voltage in short channel devices. The high electric field near the Si-SiO₂ interface can cause electrons or holes to gain sufficient energy to overcome the interface potential and enter into the oxide layer. In this phenomenon known as hot carrier effect, the electron injection is more likely to occur than the hole as electron has both lower effective mass and barrier height than hole. These carriers trapped in the oxide layer change the threshold voltage of the device and consequently the subthreshold current. Proportionate scaling down of the supply voltage with the device dimension is one possible way of controlling this leakage.