Power Dissipation and Interconnect Roadmap

Since the invention of integrated circuits by Jack Kilby few decades ago, the number of transistors in a die has continuously doubled every 24 months. This is the famous Moore’s law, which is still relevant today. Sustaining this trend has been fuelled by the abilities of the chip designers to cramp more transistors together. As noted above, it has made the designs denser but has introduced problems like power dissipations and interconnects noise. From many indications, the CMOS technology remains the most elegant technology for making chips owing to its low power static dissipation and ease of integration when compared with technology like bipolar junction transistors (BJT). This implies that it would be in use in the foreseeable future and battling the associated problems provides a huge challenge to the stakeholders.

State of the art CMOS technologies are well below 100-nanometer transistor feature size. Products made based on 65-nanometer process have already hit the market. 45-nanometer and 32-nanometer CMOS processes are expected before 2008 and 2010 respectively. This ambitious strategy of transistor miniaturization translates to making interconnects that are thinner as well as scaling the system supply power.

To make these systems appealing to the customers, there are tight budgets in power consumption and other parameters. For instance, the ITRS (2005) forecasts an allowable maximum power for battery (low cost/handheld) operated systems of 2.8W in 2005 to only 3W in 2020 [This is a very tight budget considering the expected advancements and complexities in these systems].

Within this period, the power supply for high performance systems is expected to scale down by 36% while the allowable maximum power for high performance (with heatsink) devices will increase by only 19%. The underlining consequence of this scaling would be more dominant short channel effects (SCE) and gate leakage current partly due to shorter features sizes and thinner gate oxide thickness respectively. Besides, problems associated with controlling the threshold voltage as a result of non-uniform doping as technology scales will be a major issue.

Similarly, the effect of feature size reduction affects the interconnect performance. The decrease in interconnection width and thickness increases resistance while smaller spacing progressively increases the circuit capacitance. This increase in resistance and capacitance are not desirable in the chip wires. These effects have resulted to increased role of interconnect in integrated circuit design and development. As the fringing field component of wire capacitance does not vary with feature size, when the three wire dimensions are scaled by the same scaling factor, the interconnect delay is not affected. But in reality, the scalings of the wire dimensions are not unified by the same scale factor.

Furthermore, by packing more circuits on a single die made possible by the smaller sizes of the transistors, the numbers of long interconnections are significantly increased. The resulting effect is that the interconnect delay grows bigger and even more than the gate delay of the transistor. With continuous reduction in the feature size, interconnect noise and delay will continue to be a major issue. Aluminum, once the main material for interconnect has long been replaced by copper, which has a lower resistivity. But with time, the performance of copper/low-k interconnects will become inadequate to meet the speed and power dissipation goals of highly scaled ICs.

So what is the future? The ITRS proposes an early availability of high-k gate dielectrics in order to meet the stringent gate leakage especially in low power devices. It also stated that development of low dielectric constant (low-?) material together with low-resistivity metal system would become critical for signal propagation delay reduction. Nonetheless, it acknowledges that accessing the road map is a ‘red brick’, i.e. ‘no known solution’ at least within this decade. In many instances, nanotechnology has been projected to supersede CMOS technology unless the challenges are overcome.

Notwithstanding, the challenges of interconnect and power dissipation calls for new system architecture, new materials and innovative optimization tools that would help to accurately model the complex relationships that exist in the system at nanometer regime. The chip makers have vigorously used new materials to reduce interconnect capacitance ( eg, Intel has used low-k carbon doped oxide dielectric to obtain lower interconnect capacitance) in their newer processes. Aggressive new trends would certainly emerge in the future if the demise of Moore’s law should be delayed