Power dissipation and interconnect noise challenges in nanometer CMOS technologies
Abstract
The invention of the complementary metal oxide semiconductor (CMOS) integrated circuit (IC) is a major milestone in the history of modern industry and commerce. It has driven revolutionary changes in computing due to its performance, cost, and ease of integration. But as the size of the transistors reduce into the nanometer scale, so many challenges occur with the reliability and performance of the systems. In the past few decades, the advancement of chip performance has come through increased integration and complexity on the number of transistors on a die. However, this progress has been followed with increased power dissipation and interconnection noise in circuits. Both are costly in terms of shorter battery life, complex cooling and packaging methods, and degradation of system performance.
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Ekekwe, N.;
This paper appears in: Potentials, IEEE
Issue Date: May-June 2010
Volume: 29 Issue:3
On page(s): 26 – 31
ISSN: 0278-6648
Digital Object Identifier: 10.1109/MPOT.2010.935825
Date of Current Version: 06 May 2010
Sponsored by: IEEE
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5458467
