Nanometer CMOS – The Challenges Ahead

Nanometer CMOS – The Challenges Ahead

The invention of complementary metal oxide semiconductor (CMOS) integrated circuit is a major milestone in the history of modern industry and commerce. It has driven revolutionary changes in computing due to its performance, cost and ease of integration. But as the size of the transistors scale down into the nanometer regime, so many challenges occur on the reliability and performance of the systems.

 

Signal integrity and power problems are noticeably among the major ones. In the past few decades, the advancement of the chip performance has come through increased integration and complexity on the number of transistors on a die. Though supply and threshold voltages have been scaled for every CMOS generation, the power dissipation and interconnect noise have continued to increase. This trend is costly in terms of shorter battery life, complex cooling and packaging methods, and degradation of system performance.

 

Power dissipation in CMOS circuits involves both static and dynamic power dissipations. In the submicron technologies, the static power dissipation, caused by leakage currents and subthreshold currents contribute a small percentage to the total power consumption, while the dynamic power dissipation, resulting from charging and discharging of parasitic capacitive loads of interconnects and devices dominates the overall power consumption.

 

But as technologies scale down to the nanometer regime (ultra deep submicron (UDSM)), the static power dissipation becomes more dominant than the dynamic power consumption. And despite the aggressive downscaling of device dimensions and reductions of supply voltages, which reduce the power consumption of the individual transistors, the exponential increase of operating frequencies results in a steady increase of the total power consumption.

 

Interconnect noise and delay emanate during distribution of on chip signals and clocks using local, intermediate and global wires. Introduction of repeaters on the interconnect paths mitigate the effect of delay at the expense of chip area and power consumption. With technology downscaling, interconnect resistance and capacitance increases the propagation delay. As the cross section of chip interconnect is reduced, the resistance per unit length is increased. Closer routing and wire reduction have increased chip interconnect capacitance and resistance effects respectively.

 

The relationships between interconnect delay and technology show that downscaling of feature size increases circuit propagation delay. It is evident that as the technology scales, the gate delay decreases but with increase in interconnect delay. At around 0.12um technology, the interconnect delay has become exceedingly dominant over the gate delay. This increase is worrisome to chip designers in the quest for continuous circuit miniaturization and denser integration in CMOS technology.

 

The International Technology Roadmap for Semiconductor (ITRS) 2005 forecasts continuous reduction in feature size to be alive and well into the future. With this continuous scaling, if interconnect noise and power dissipation, especially the static power dissipation, are not controlled and optimised, they promise to become major limiting factors for system integration and performance improvement.

 

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