17 Technical Citations On Our Journal Article Predicting The Challenges Of Ultra Deep Submicron CMOS Technologies

This piece was written in 2006 and was well received in the technical community. It has been been published in IEEE Potentials. In it, we predicted the challenges of the ultra deep submicron CMOS technologies. Then we offered roadmaps to solving them. We just checked today; 17 people have cited it. Notice that due to how Google Scholar works, there are usually more citations than recorded. A single mistake in the title or the way the name is written will throw Google algorithms into limbo. But even the 17 is not bad. To get cited in a technical journal is not a piece of cake or ice cream. This is the original paper in case you want to read. In it, we modeled the transistor down to the 64nm CMOS when it was just coming. In short, this work was one of the earliest to have done it.

 

[PDF] from afrit.orgN Ekekwe… – Microelectronics journal, 2006 – Elsevier As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations grow exponentially and become an increasingly dominant component of the total power dissipation in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides

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[PDF] from psu.eduV Nélis, J Goossens, R Devillers… – … Conference on Sensor …, 2008 – computer.org

In this paper, we address the power-aware scheduling of sporadic constrained-deadline hard

real-time tasks us- ing dynamic voltage scaling upon multiprocessor platforms. We propose two

distinct algorithms. Our first algorithm is an off-line speed determination mechanism which

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